Method of producing CMOS transistors and related devices

ABSTRACT

A method for making CMOQ transistors and associated devices. The method is used to make transistors of a first type and a second type in CMOS technology in an active layer. The method etches regions of the active layer or making them inactive so as to define active islands designed to form sources, channels of determined width, and drains of the transistors of the first type and second type respectively, covers at least two active islands with an insulating layer and covers the insulating layer with a conductive layer, and sequentially etches all the gates of the transistors of the first type and then all the gates of the transistors of the second type. The associated devices includes CMOS transistor devices obtained by the method. Such a method may particularly find application to devices for the addressing and control of active matrix liquid crystal displays.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the making of MOS transistors, a devicecomprising MOS transistors obtained by a method such as this and adevice for the addressing and control of an active matrix made withdevices such as these.

The invention pertains especially to an addressing and control devicefor an active matrix liquid crystal display.

The invention relates especially to the field of large-scale consumerelectronics. It can be used to make electronic circuits with CMOScomplementary transistors made of polycrystalline silicon. Thesetransistors may comprise a lightly doped gate-edge region.

The invention can be applied to low-temperature methods (Tmax<450° C.)compatible with non-refractory and non-crystalline substrates

2. Discussion of the Background

AMLCDs or Active Matrix Liquid Crystal Displays are made, according toprior art techniques, on a glass plate. The addressing of the activematrix liquid crystal displays is presently done by the integration ofthin-film transistors on the glass plate. These TFT transistors are madeout of amorphous hydrogenated silicon aSi:H. TFT transistors of thistype have low electron mobility, in the range of 0,5 cm² V⁻¹ s⁻¹. Thetechnology implemented to make them cannot be used to obtain acomplementary logic circuitry. These constraints limit the use of such atechnology to the making of the transistors needed to address the pixelsof the screen. The management of the screen includes the selection ofthe lines, shaping and the presentation of the video. data on thedifferent columns. The making of a device to carry out screen managementrequires the use of another technology, for example a technique totransfer silicon integrated circuits to the periphery of the glass slab.

To overcome the drawbacks of the technologies using amorphous silicon,the technologies are developing towards the use of thin-filmpolycrystalline silicon. The value attached to the use of thin-filmpolycrystalline silicon lies in the possibilities offered by thismaterial for making high-quality electronic circuits on non-refractoryand non-crystalline substrates.

The chief known applications lie in the addressing of active matrixliquid crystal displays.

Polycrystalline silicon enables the low-temperature manufacture of Ntype and P type TFTs with high values of mobility in the range of 100and 50 cm² V⁻¹ s⁻¹ respectively. Polycrystalline silicon can thereforebe used to make CMOS circuits with performance characteristicscompatibles with the addressing of flat screens. The integration of allor part of the peripheral addressing electronics results in a relativedecrease in the cost of the screen related to the disappearance of theintegrated circuits. However, this is true only inasmuch as the increasein the complexity of the circuits made on the glass plate do not resultin any major drop in manufacturing efficiency levels. The manufacturingefficiency is directly related to the number of masks used for themaking of the electronic circuits.

The basic known method for the making of CMOS circuits on insulatorsubstrates (for example of the SOI or Silicon On Insulator type) callsfor at least six masks corresponding to the following steps:

definition of the silicon islands,

definition of the gate of the transistors,

definition of the N type implantation region,

definition of the P type implantation region,

opening of the contact holes,

definition of the metal.

SUMMARY OF THE INVENTION

The aim of the invention is to reduce the number of masks needed to makeCMOS technology circuits as compared with known methods.

To this end, an object of the invention is a method for makingtransistors of a first type and a second type by CMOS technology in anactive layer, characterized in that it consists in:

etching regions of the active layer or making them inactive so as todefine active islands designed to form the sources, the channels ofdetermined width and the drains of transistors of the first type andsecond type respectively,

covering at least the active islands with an insulating layer and then aconductive layer,

sequentially etching all the gates of the transistors of the first typeand then all the gates of the transistors of the second type.

The gate of each transistor controls the transistor by enabling thecontrol of the channel of this transistor.

The advantage of the method according to the invention is that itreduces the number of masks and the number of implantation steps.

In the basic known method, the gates of the NMOS and PMOS transistorsare etched simultaneously. The N+ and P+ contact regions are obtained byion implantation. They are self-aligned with respect to the gate edges:the gate plays the role of a mask. For the N type transistors, thissituation leads to intense electrical fields in the gate edge channel.The intense electric fields induce either instability in thecharacteristics when the gate bias is positive or major leakage currentswhen the gate bias is negative. The instability of the characteristicsis related to the generation of hot electrons in the channel and thecreation of interface defects when these hot carriers interact with thehydrogen atoms, making the defects of the SiO₂/Si interface passive. Theleakage currents originate in the intense electrical field of thereverse-biased drain-channel junction. The level of the leakage currentsthen depends exponentially on the drain-source and gate-source voltages.

To attenuate these intense electrical fields, a particular region ismade at the gate edge. This region has the characteristic of being morelightly doped than the rest of the channel. It is called an LDD regionor lightly doped drain region. The LDD region is an N− type region foran N type transistor N. The extension of the LDD region is in the rangeof 10% of the length of the channel, i.e. about 0,1 μm formonocrystalline silicon technologies and about 0,5 for polycrystallinesilicon technologies. In monocrystalline technology, the LDD region isobtained by making a gate edge spacer or dielectric space. The spacer isobtained by appropriate deposition and anisotropic etching of adielectric film. This technology is not directly applicable tolarge-surface substrates.

In known polycrystalline silicon technologies, the making of the LDDregion requires a special mask and a particular step of implantation.This takes the number of masks needed to seven and the number ofimplantation steps to three. The invention reduces the number of masksneeded to five and the number of implantation steps to two. Theinvention provides for a self-alignment of the LDD region and permits acheck on the dose of dopant independently of the extension of the LDDregion.

In the known polycrystalline silicon technologies, the LDD region isobtained by a light dose implantation self-aligned on the gate. Afterthis, the LDD region is protected by resin during the heavy-doseimplantation with dopant, namely N+ type implantation for an N typetransistor, for example phosphorus. This may give rise to additionaltechnological difficulties related to the heating of the resin under theflow of ions when the method is carried out on large-sized glass plates.This risk is totally absent in a method according to the invention. Thelayer of protective resin is removed before the heavy-dose implantationof a dopant.

An object of the invention is also a device for the addressing andcontrol of an active matrix liquid crystal display made with CMOStransistors obtained by a method according to the invention.

The addressing and control device comprises an addressing device and acontrol device. The addressing device is a device with CMOScomplementary transistors.

The control device is a device that does not require complementarytransistors. It is preferably made with N type transistors. When thesetransistors are provided with an LDD region, according to a particularembodiment of the invention, they have the advantage of having a verylimited leakage current. This characteristic is particularly importantfor large-sized active matrix screens. Each pixel of the screen iscontrolled by means of the gate of a transistor. Between two operationsfor refreshing a row of the matrix, the state of a pixel is held bymeans of the memory function obtained by the association of thecapacitance of the pixel and the off state of the transistor, providedhowever, that the drain-source leakage current does not have the time tohave any notable effect on the charge of the capacitance. Thus, thedrain-source leakage current of the control transistors has an immediateeffect on the quality of the image. In particular, the greater thedrain-source leakage current, the more it results in a large

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be understood more clearly and its othercharacteristics and advantages will appear from the followingdescription given by way of a non-restrictive illustration made withreference to the appended figures of which:

FIG. 1 shows the steps of the method according to the invention

FIGS. 2a, 2 b, 2 c show steps in the definition of active islands andthe deposition of layers for a first or second type of transistor,

FIGS. 3a, 3 b, 3 c, 3 d and 3 e show steps in the etching of the gatesfor a transistor of the first type,

FIGS. 4a, 4 b, 4 c, 4 d and 4 e show steps in the etching of the gatesfor a transistor of the second type,

FIGS. 5a and 5 b respectively show a schematic top view of a gate of afirst type and a gate of a second type respectively.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates the different steps in the carrying out of the methodaccording to the invention. The method can be applied to a substrate onwhich an active thin layer is made. To make transistors of a first andsecond type, using CMOS technology in the active layer, the method takesplace in several steps. In a first step, the method consists in defining1 active islands. The definition 1 of the active islands is done eitherby the etching of the regions of the active layer or by making regionsof the active layer inactive. The active islands are designed to formthe sources, channels and drains of the transistors of the first typeand second type respectively. In a second step, the method consists ofthe deposition 2 of two layers. A first layer covers at least the activeislands. A second conductive layer covers the first layer. The secondconductive layer is designed to form the control gate of thetransistors. In a third step, the method consists of the sequentialetching 3 of all the gates of the transistors of the first type and allthe gates of the transistors of the second type. The etching of all thegates of the transistors of a given type is done by means of aparticular mask. The mask reproduces the gates of the transistors of thegiven type and masks the implantation regions of the transistors of theother type. With the same mask, it is thus possible to perform dopingoperations for a given type of transistor.

FIGS. 2a, 2 b and 2 c illustrate the steps for the definition 1 ofactive islands and deposition 2 of the first and second layers for afirst or second type of transistor. Hereinafter in the description ofthe method, the first type corresponds to the N type and the second typeto the P type. This choice corresponds to a first mode of implementationof the method. The N type transistors and the P type transistors aremade by the first mode of implementing the method according to theinvention, on a same substrate. The substrate 4 preferably consists ofglass on which there is deposited a preparation layer 5 designed toobtain a surface condition favorable to subsequent treatment. Accordingto the prior art, this preparation layer may be made of silica SiO₂. Anactive layer 6 is deposited on the preparation layer 5. The active layer6 consists for example of polycrystalline silicon. A layer of protectionresin 7 is deposited on the active layer 6.

A first mask, not shown, reproduces the active islands to be preservedin the active layer 6. These are active islands with which it ispossible, subsequently, to make the sources, channels and drains of thetransistors. The active islands are made by known techniques, forexample by etching.

According to the illustration in FIG. 2b, the active islands 6 are madeby removing material. In one variant of this technique, the regions notmasked by the first mask are made inactive, for example by passivation,rather than being eliminated. Once the active islands 6 have been made,the resin layer 7 is eliminated by known techniques, for example aqueousbaths.

In a following step, the insulator layer 8 and the conductive layer 9are deposited in succession. The insulator layer 8 is, for example, asilicon oxide, especially SiO₂. The insulator layer 8 has a thickness of50 to 150 nm. According to the illustration in FIG. 2c, the insulatorlayer 8 covers the totality of the substrate. In alternative modes ofimplementation of the method, the insulator layer 8 covers at least theactive islands 6. The conductive layer 9 is made, for example, with N+doped polycrystalline silicon or with a metal, for example tungsten (W),molybdenum (Mo) or aluminium (AI). Between the different metals, thechoice will preferably be that of aluminium which is the least resistivemetal. The conductive layer 9 has a thickness ranging from 150 to 300nm. It is designed to form the gate of the transistors.

FIGS. 3a, 3 b, 3 c, 3 d, 3 e, 4 a, 4 b, 4 c, 4 d and 4 e, illustrate thestep of sequential etching of all the gates of the N type transistorsand of all the gates of the P type transistors.

In a first mode of implementation of the method according to theinvention, the N type transistors and the P type transistors are made onone and the same substrate. The first mode of implementation of themethod is illustrated in FIGS. 3a to 3 e and 4 a to 4 e which representthe different regions of one and the same substrate. FIGS. 3a to 3 eillustrate a region of implantation an N type transistor while FIGS. 4ato 4 e illustrate a region of implantation of a P type transistor.

FIGS. 3a and 4 a respectively show a substrate 4 covered with apreparation layer 5 on which an active island 6 is etched. The activeisland 6 is buried beneath an insulating layer 8, which is itselfcovered with a conductive layer 9. FIGS. 3a and 4 a respectively take upthe method as illustrated in FIG. 2c.

Between FIGS. 3a, 3 b, and 4 a, 4 b respectively, a protective resinlayer 7 has been deposited to protect certain regions. A second mask,not shown, defining the gates of the N type transistors is used to etchsolely the gates 9 of the N type transistors, FIG. 3b. During theetching of the gates of the N type transistors, the protective resinlayer 7 remains intact on the P type transistors. FIG. 4b gives anillustration of it. The etching of the gates of the N type transistorsconsists of an etching done isotropically as illustrated in FIG. 3b. Itis followed by an etching done anisotropically as illustrated in FIGS.3c and 4 c. The technique of isotropic etching implemented may be eithera wet etching technique or a dry etching technique. If the conductivelayer 9 is made out of molybdenum Mo or aluminium Al, the wet etchingtechnique is generally used (in this technique, the circuit to be etchedis steeped in a solution). If the conductive layer 9 is made out ofpolycrystalline silicon or tungsten W, the dry etching technique isgenerally chosen. It consists of the introduction of the circuit to beetched into a plasma-filled chamber. Isotropic etching opens out anover-etched depth L_(ov). The over-etching depth L_(ov) is controlled soas to be between 0.2 and 2 μm in the case of a dry etching technique andbetween 0.5 and 2 μm in the case of a wet etching technique. Theisotropic etching of the conductive layer 9 is done until the insulatorlayer 8 is reached.

The second mask is maintained during the anisotropic etching. Theanisotropic etching is done solely by a dry etching method. Thisoperation consists in etching the insulator layer 8 in a way that isself-aligned with the resin 7 until the active island 6 is reached. Thesuccession of the two etchings, namely the isotropic etching and theanisotropic etching, gives a step at the gate edge, constituted by theinsulator layer 8.

The width of the step is equal to the over-etching depth L_(ov). LetL_(r) be the length of the protective resin layer 7 etched during theoperation of etching the gate illustrated by FIG. 3b. The length L ofthe gate, etched in the conductive layer 9, is given by therelationship:

L=L _(r)−(2. L _(ov))  (1)

Since the second mask reproduces only the gates of the N typetransistors, the protective resin layer 7 maintains a protection, asshown in FIGS. 4b and 4 c, over the P type transistors. After theanisotropic etching operation, the protective layer of resin 7 isremoved.

After the etching of the gates of the N type transistors and the etchingof the insulator steps, the method consists of the doping of the sourcesand drains of the N type transistors. For the N type transistors, thedopant used is N type doping, for example phosphorus. The dopingoperation is done on the surface without any mask or protective resin.The implantation regions of the P type transistors are automaticallyprotected during the operation of doping the N type transistors: themetal layer 9 totally covers the implantation regions of the P typetransistors and protects them from the dopant.

In the first mode of implementation of the method, the method comprisesa particular operation. This operation consists of the implantation of alightly doped region, called an LDD, at the edge of the gate of the Ntype transistors. It is illustrated by FIGS. 3d and 4 d. According tothis operation, the operation of doping with an N type dopant consistsof the sequential implantation of the following:

a heavy dose of the dopant at low energy, i.e. for example a dose ofphosphorus with a density D=10¹⁵ cm² in a field with an energy valueE=15 kev,

a light dose of the dopant at high energy, i.e. for example a dose ofphosphorus with a density D=10¹³ cm² in a field with an energy levelE=100 kev.

The implantation of a heavy dose at low energy causes the dopant topenetrate up to a depth of about 40 nm. Since this depth is smaller thanthe thickness of the insulator layer 8, the part of the channel 10located beneath the insulator layer is protected by this layer duringthis implantation.

The implantation of a light dose at high energy has an implantation peakat about 150 nm from the surface. It leads to a penetration of thedopant, beyond the insulator layer 8, in a region 11 of the channel 10not protected by the gate 9. The active 35 islands 6 of the P typetransistors are totally protected by the superimposition of theinsulator layer 8 and of the conductive layer 9, as illustrated by FIG.4d.

The source 12 and the drain 13 of a transistor are on either side of thegate 9 in the prolongation of the channel 10. During each of theprevious two implantations, the dopant penetrates the regions of theactive island that are not masked by the gate 9 enabling the source 12and the drain 13 to be doped.

With the protective resin layer 7 having been eliminated before thedoping operation, the method is advantageously used to carry out theimplantation of a heavy dose of phosphorus without having any residualresin on the substrate 4. It is indeed known that an implantation with aheavy dose of phosphorus (atomic mass 29) is capable of causing theglass plate to get heated to a temperature of over 120-150° C. Theheating jeopardizes the operation of eliminating the layer of protectiveresin, while leaving organic residues on the surface.

The method then consists of the operation of etching the gates of the Ptype transistors and the operating of doping with a P type dopant. Inaccordance with the illustration in FIGS. 3e and 4 e, the methodconsists of the deposition of a protective layer of resin 7 on all thetransistors, both the N type transistors and the P type transistors. Athird mask (not shown) reproducing the gates of the P type transistorsand masking all the N type transistors is used to etch the gates 9 ofthe P type transistors.

The etching operation is of the anisotropic type. It can be used toself-align the etching of the conductive layer 9 and of the insulatorlayer 8 on the protection resin 7.

The doping operation makes it possible to dope the sources 12 and thedrains 13 of the P type transistors. The doping is P type doping. Forexample, it may be boron. The doping operation consists in implanting ahigh doses of dopant with very low energy, for example, a density D=10¹⁵cm² of dopant with an energy E=5 kev. During the doping operation, the Ntype transistors are protected by the protection resin layer 7. Theheating problem encountered with phosphorus is almost non-existent inthe case of boron, firstly because of the difference in atomic massbetween boron (atomic mass 10) and phosphorus (atomic mass 29) andsecondly because of the energy brought into play which is lower duringthe implantation of boron.

FIGS. 5a and 5 b respectively show a top view of the N type transistorof FIG. 3d and the P type transistor of FIG. 4e respectively.

FIGS. 5a and 5 b show a truncated view of the N type transistor and theP type transistor. FIGS. 5a and 5 b give a schematic view of therelative arrangement of the gate and channel of the transistor.

The N type transistor in FIG. 5a has an insulator step 8. FIGS. 5a et 5b cover a part of the channel 10 of the transistor. The channel 10 is inthe prolongation of the source 12, not shown, and of the drain 13, notshown.

The gate 9 has a width I_(g), The channel has a width I_(d). The etchingof the gate 9 is done in such a way that I_(g)>I_(d), according to thetechniques of those skilled in the art.

The operation of doping the sources and drains of the N type transistorshas been described with reference to FIG. 3d. Another embodiment of thedoping operation can be implemented. It consists in:

performing a first operation of surface doping with the specifieddopant,

eliminating the insulator step on the edge of the conductive layer,

performing a second surface doping operation with the specified dopant.

The making of the transistors, both N type and P type transistors, iscomplemented by an operation of passivation and an operation of openingcontacts. These operations are performed according to known techniques.They require a fourth mask and a fifth mask.

In a second mode of implementation of the method according to theinvention, the transistors of the first type are P type transistors andthe transistors of the second type are N type transistors.

In a third mode of implementation of the method according to theinvention, the method does not comprise the particular operation whichconsists in implanting an LDD region. The structures obtained arestructures of the type known as offset structures.

In a fourth mode of implementation of the method according to theinvention, the transistors of the second type are made on a substratedifferent from the substrate on which the transistors of the first typeare made.

An addressing and control device for an active matrix liquid crystaldisplay according to the invention is made with CMOS transistorsobtained by a method according to the invention. The addressing andcontrol device comprises an addressing device and a control device.

The addressing device is a device using CMOS complementary transistors.In a first embodiment, the N type and P type transistors are obtainedaccording to the third mode of implementation of the method. The otherembodiments of the addressing device are made by means of the othermodes of implementation of the method for making transistors accordingto the invention.

The control device is a device that requires transistors having a lowleakage current. It is made with transistors provided with an LDDregion, preferably of the N type. The N type transistors are madeaccording to the first mode of implementation of the method. Since thecontrol device does not necessitate any complementary transistors, thefirst mode of implementation of the method may be limited solely to themaking of N type transistors. The P type transistors are made accordingto the second mode of implementation of the method. Since the controldevice does not necessitate any complementary transistors, the firstmode of implementation of the method may be limited solely to the makingof P type transistors.

The invention has been described with reference, for example, to a glasssubstrate. The invention can be applied to other types of substrate suchas plastic or quartz substrates.

The method according to the invention takes place at a given temperatureincluded in a certain range. A glass substrate has a determined range oftemperature corresponding to it. A plastic substrate has another rangeof temperature, lower than the determined range of temperature,corresponding to it. A quartz substrate has yet another range oftemperature, higher than the determined temperature, corresponding toit.

What is claimed is:
 1. Method of making transistors of a first type anda second type by CMOS technology in an active layer, characterized inthat it comprises: etching regions of the active layers or making theminactive to define active islands designed to form sources, channels ofdetermined width and drains of the transistors of the first type andsecond type, covering the active islands with an insulating layer,covering the insulating layer with a conductive layer, covering theconductive layer with a resin protective layer, and sequentially etchingthe insulating layer, the conductive layer, and the resin protectivelayer to form all gates of the transistors of the first type and thenall gates of the transistors of the second type.
 2. Method for makingtransistors according to claim 1, characterized in that the etching allthe gates of the transistors of the first type comprising: defining amask reproducing the gates of the transistors of the first type andmasking the transistors of the second type, etching the gates of thetransistors of the first type with the mask, removing the mask and inthat the method comprises: carrying out a doping operation with adetermined dopant.
 3. Method for making transistors according to claim2, characterized in that the etching of the gates of the transistors ofthe first type comprises in isotropically over-etching the conductivelayer until the insulator layer is reached and until a determinedover-etching depth is opened, and is followed by an anisotropic etchingof the insulator layer until an active island is reached, the isotropicover-etching and anisotropic etching operations being used to obtain, onthe edge of the conductive layer, an insulator step whose width is givenby the over-etching depth.
 4. Method for making transistors according toclaim 2, characterized in that the doping operation comprises: anoperation of low-energy doping and an operation of high-energy doping.5. Method for making transistors according to claim 2, characterized inthat the doping operation comprises: carrying out a first dopingoperation with the determined dopant, eliminating the step on the edgeof the conductive layer, carrying out a second doping operation with thedetermined dopant.
 6. Method for making transistors according to claim1, characterized in that the etching of all the gates of the transistorsof the second type comprises: defining a mask reproducing the gates ofthe transistors of the second type and masking the transistors of thefirst type, etching the gates of the transistors of the second type withthe mask and in that the method consists in: carrying out, with themask, an operating of doping with a determined dopant.
 7. Method formaking transistors according to claim 1, characterized in that thetransistors of the first type are N type transistors and the transistorsof the second type are P type transistors.
 8. Method for makingtransistors according to claim 7, characterized in that the dopant isphosphorus.
 9. Method for making transistors according to claim 1characterized in that the transistors of the first type are P typetransistors and the transistors of the second type are N typetransistors.
 10. Method for making transistors according to claim 9,characterized in that the dopant is boron.
 11. Method of makingtransistors according to claim 1, wherein sequentially etching comprisessequentially etching the resin protective layer to form all gates of thetransistors of the first type using a first mask and then all gates ofthe transistors of the second type using a second mask.
 12. Method formaking transistors of a first type and a second type by CMOS technologyin an active layer, characterized in that it comprises: etching regionsof the active layers or making them inactive to define active islandsdesigned to form sources, channels of determined width and drains of thetransistors of the first type and second type, covering the activeislands with an insulating layer and covering the insulating layer witha conductive layer, sequentially etching all gates of the transistors ofthe first type and then all gates of the transistors of the second type,wherein the gate of each transistor has a width greater than adetermined width of the channel between the drain and the source of thecorresponding transistor.
 13. Method for making transistors according toclaim 12, wherein sequentially etching comprises sequentially etching aresin protective layer to form all gates of the transistors of the firsttype using a first mask and then all gates of the transistors of thesecond type using a second mask.